Back end of line process integrated optical device fabrication

ABSTRACT

An integrated optical device fabricated in the back end of line process located within the vertical span of the metal stack and having one or more advantages over a corresponding integrated optical device fabricated in the silicon on insulator layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims priority from U.S. patent application Ser.No. 16/134,086 filed Sep. 18, 2018, now allowed, which is a continuation of and claims priority from U.S. patent application Ser. No. 15/826,897 filed Nov. 30, 2017, now U.S. Pat. No. 10,101,533, which is a continuation of and claims priority from U.S. patent application Ser. No. 14/830,046, filed Aug. 19, 2015, now U.S. Patent No. 9,851,506, which is a continuation-in-part of and claims priority to U.S. patent application Ser. No. 14/798,780, filed Jul. 14, 2015, issued as U.S. Pat. No. 9,588,298, which claims the benefit of provisional U.S. Provisional Application No. 62/170,772, filed Jun. 4, 2015, each of which is hereby incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present disclosure relates to integrated optical devices and their fabrication and particularly to integrated optical devices fabricated using back end of line processes.

BRIEF SUMMARY

According to a first broad aspect disclosed is a method of integrated optical device fabrication including: forming a waveguide portion of an optical device within a vertical span of a metal stack of an integrated semiconductor chip as part of a back end of line fabrication process.

In some embodiments, forming the waveguide portion of the optical device comprises forming the waveguide portion of a material having a first index of refraction greater than a second index of refraction of an oxide material surrounding the waveguide portion. In some embodiments, forming the waveguide portion of the optical device includes doping the oxide material to form a doped waveguide. In some embodiments, doping the oxide material to form the doped waveguide includes doping utilizing at least one of ion implantation and diffusion and wherein the doping utilizes a material comprising at least one of B, F, Al, Ti, As, P, Er, Ni, Si, Cu, Zn, Ge, N, Zr, Nd, and Yb. In some embodiments, forming the waveguide portion of the optical device includes forming an optical waveguide in one of an etch stop layer, a chemical mechanical planarization (CMP) stop layer, and a dielectric material layer used in fabricating the metal stack. In some embodiments, the waveguide portion of the optical device comprises at least one of silicon nitride, poly-silicon, and silicon oxynitride (SiON). In some embodiments, forming the waveguide portion of the optical device includes material deposition within the vertical span of the metal stack. In some embodiments, material deposition includes deposition of at least one of silicon nitride, amorphous silicon, poly-silicon, silicon oxynitride (SiON), silicon-germanium (SiGe), SiO₂, silicate glass, and germanium (Ge). In some embodiments, material deposition includes deposition of a silicate glass comprising SiO₂, and at least one of P₂O₅, B₂O₃, F, Al₂O₃, As₂O₃, GeO₂, N₂, TiO₂, ZrO₂, Nd₂O₃, Er₂O₃, and Yb₂O₃. In some embodiments, the waveguide portion of the optical device comprises at least one of silicon nitride, poly-silicon, and silicon oxynitride (SiON), amorphous silicon, silicon-germanium (SiGe), SiO₂, silicate glass, and germanium (Ge).

According to a second broad aspect, disclosed is an integrated optical device including at least one waveguide portion fabricated in a back end of line fabrication process formed within a vertical span of a metal stack of an integrated semiconductor chip.

In some embodiments, the at least one waveguide portion comprises a material having a first index of refraction greater than a second index of refraction of an oxide material surrounding the at least one waveguide. In some embodiments, the at least one waveguide portion comprises a doped waveguide comprised of doped oxide material. In some embodiments, the doped waveguide is one of an ion implantation doped waveguide and a diffusion doped waveguide and wherein the doped waveguide is doped with a material comprising at least one of B, F, Al, Ti, As, P, Er, Ni, Si, Cu, Zn, Ge, N, Zr, Nd, and Yb. In some embodiments, the at least one waveguide portion includes a portion of one of an etch stop layer, a chemical mechanical planarization (CMP) stop layer, and a dielectric material layer used in fabricating the metal stack. In some embodiments, the at least one waveguide portion includes at least one of silicon nitride, poly-silicon, and silicon oxynitride. In some embodiments, the at least one waveguide portion includes at least one of deposited silicon nitride, deposited poly-silicon, deposited SiON, deposited SiGe, deposited Ge, deposited SiO₂, deposited silicate glass, and deposited amorphous silicon. In some embodiments, the at least one waveguide portion comprises deposited silicate glass comprising SiO₂ and at least one of P₂O₅, B₂O₃, F, Al₂O₃, As₂O₃, GeO₂, N₂, TiO₂, ZrO₂, Nd₂O₃, Er₂O₃, and Yb₂O₃. In some embodiments, the at least one waveguide portion is located vertically between any at least two of etch stop layers, chemical mechanical planarization stop layers, and dielectric layers used for fabricating the metal stack. In some embodiments, the at least one waveguide comprises at least one of silicon nitride, poly-silicon, and silicon oxynitride (SiON), amorphous silicon, silicon-germanium (SiGe), SiO₂, silicate glass, and germanium (Ge).

The foregoing and additional aspects and embodiments of the present disclosure will be apparent to those of ordinary skill in the art in view of the detailed description of various embodiments and/or aspects, which is made with reference to the drawings, a brief description of which is provided next.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings.

FIG. 1 is an example of doped oxide waveguides fabricated as part of the back end of line fabrication process.

FIG. 2 is an example of using the silicon nitride (SiN) etch stop layers in standard CMOS back end of line fabrication process to create integrated optical devices.

FIG. 3 is an example of deposited SiN, poly-Si or a-Si (amorphous silicon) optical devices fabricated between two metal layers during back end of line fabrication processes.

FIG. 4A is a vertical cross section of an example coupling between optical devices formed in the standard silicon front end and optical devices fabricated as part of the back end of line fabrication process.

FIG. 4B is a top plan view of the coupling of FIG. 4A.

FIG. 4C is a simulated electric field of an optical signal propagating through the coupling of FIGS. 4A and 4B.

FIG. 5 is a perspective view of an example vertical coupler coupling an optical device built in the front end with an optical device formed in the back end of line fabrication process.

While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments or implementations have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of an invention as defined by the appended claims.

DETAILED DESCRIPTION

Currently, known integrated silicon photonic devices are typically built on an SOI (silicon on insulator) layer in the front end. This is the same silicon layer in which modulators, detectors, transistors, diodes, and other semiconductor devices are formed, located above the buried oxide (BOX) layer serving as the insulator, and beneath the metal stack. These devices in the front end are formed as part of the front end of line (FEOL) fabrication process which includes fabrication up to but not including process steps utilized to form the metal stack. Other known techniques involve integrated silicon photonic devices and their fabrication in the back end of the traditional electronics wafer. These optical devices, being in the back end, are formed outside and on top of the metal stack in deposited poly silicon, SiN, or other optically suitable material. These devices in the back end are formed as part of a back end deposited silicon fabrication process (BDSP) which occurs after deposition of the final passivation layer.

The back end of line fabrication process (not to be confused with the back end fabrication process), predominantly associated with fabrication of the metal interconnects of the metal stack, includes processing steps after the FEOL up to and including final passivation layer fabrication.

The dominant cost in building products using silicon photonics is the packaging. This is due to a number of factors including the tolerance required for optical connections. Although in principle reducing the complexity and cost of optical packaging can be accomplished by increasing the size of the mode at the interface of the silicon chip, because of the high confinement exhibited by the silicon layer formed in the front end, it is often costly and difficult to build devices in the front end that are capable of matching large optical modes at the interface.

A larger mode would allow larger misalignment tolerance for the same amount of misalignment loss. Silicon photonics being a traditionally a high-confinement platform, absent costly and difficult front end process modification, exhibits misalignment intolerance and a corresponding misalignment loss.

The buried oxide (BOX) layer in standard silicon photonics is about 2 micrometers thick. Due to the resulting proximity of the silicon layer, modes that are larger than 3 micrometers in diameter will have loss due to substrate coupling whether or not misalignment tolerances have been compensated for. Moreover, because the location of the silicon device layer is fixed, it is difficult to align the waveguides in different chips when they have different thicknesses and other geometric differences.

One example of an application encountering one or more the above difficulties is fiber coupling between photonic devices in an SOI layer in the front-end and the larger fiber modes of an optical fiber.

Another problem exhibited by silicon devices formed in the front end is that their optical performance is limited by the coherence length exhibited by their silicon waveguides. Because of the high index contrast between silicon and oxide, the etched sidewall roughness causes unpredictable phase shifts in the optical mode traveling in the waveguides. This unpredictability is difficult to compensate for and limits the performance of some devices. Arrayed waveguide gratings (AWGs) are an example class of optical device whose performance is degraded by this unpredictability.

There are a wide variety of chips that need to be coupled to silicon devices, for example gain chips built in III/V materials, and their modes are of different sizes and shapes. It is difficult to achieve alignment and mode size matching in both x and y required for high efficiency coupling when restricted to a single material such as the silicon of the SOI layer. Integrating optical devices utilizing materials other than silicon during front-end fabrication to achieve desired efficiencies can be difficult and costly.

In the context of the fabrication of optical devices in the back end above the metal stack, because the metal stack is usually more than 2 micrometers thick, it is difficult to couple light through the 2 micrometer gap to the silicon on insulator layer without any intermediate layers in between.

Various techniques have been developed and utilized in an attempt to avoid and/or mitigate one or more of the common problems outlined above.

Silicon nitride has been integrated into the front-end processes to allow fabrication of edgecouplers and arrayed waveguide gratings in the front end. It should be noted, however, that it is still difficult to build edgecouplers for single mode fiber, because the thickness of buried oxide (BOX) layer is usually only 2 micrometers, and the optical mode of the edgecouplers is close enough to the substrate to cause high substrate loss. Deep oxide etching and silicon etching have been utilized to remove substrate loss causing silicon under the edgecoupler, however, they are complicated processes, resulting in devices which are often fragile because of the holes and hollows created inside the chip, and have compatibility issues with further processing. Furthermore, although arrayed waveguide gratings have been fabricated in the front end on silicon and silicon nitride layers, these devices are often large, occupying a substantial footprint on the chip, increasing costs and reducing the scale of integration.

As described hereinbelow, to address one or more of the problems described hereinabove, back end of line processes of fabrication are utilized to fabricate integrated optical devices. Optical devices formed during back end of line fabrication being located within the vertical span of the metal stack, either constructed from the silicon nitride or other compatible material of an etch stop layer or simply formed between such etch stop layers either by doping, deposition, or otherwise avoid substrate loss due to their relative remoteness from the silicon handle, and generally exhibit greater flexibility in fabrication both geometrically and materially than devices fabricated in the front end. During the back end of line processes, in addition to masks for the metal interconnect layers, new masks are used to define the optical devices. This can be done by etching existing backend dielectric materials, or by depositing new materials within the vertical span of the metal stack. Compared to the attempts to achieve the same functionality in the front end, fabricating optical devices as part of the back end of line fabrication process reduces cost and complexity, potentially economizes use of material and process steps, and allows for better alignment, material interfacing, mode matching, avoiding coherence length problems, and for greater flexibility in optical packaging. It also decouples the problem of modulator design from other processes to generate different types of waveguides.

As a result of the above, performance is improved and integration scale is increased, while costs and complexity are controlled when compared to known front end fabrication.

As described hereinbelow, various types of materials and techniques may be utilized to fabricate the optical devices throughout the vertical span of the metal stack including the fabrication of vertical couplers to easily and effectively couple light to/from the silicon on insulator layer in the front end from/to various layers of the back end of line process.

With reference to FIG. 1 an example of using doped oxide waveguides formed in back end of line process to create a large mode for fiber coupling will now be described.

An integrated optical chip 100 includes a silicon substrate or silicon handle 102 on which is formed the buried oxide (BOX) layer 104. As per standard silicon on insulator fabrication processes, a silicon layer 106 is formed on top of the buried oxide layer 104. Much of the silicon layer 106 is utilized for fabrication of semiconductor devices therein, which devices are connected to each other and external contacts with use of a metal stack including metal vias 110 a, 110 b connecting metal layers 108 a, 108 b in the stack. Not shown are etch stop layers utilized in the fabrication process. Some portions of the silicon layer 106 a are utilized for fabrication of integrated optical devices. Above the silicon layer 106 are various oxide layers 105 which have been deposited during the metal layer fabrication process. Optical waveguides 120 a, 120 b are formed in the oxide layers 105 within the vertical span of the metal stack through a process of doping the oxide 105 itself. In accordance with the embodiment depicted in FIG. 1, doping can be performed via ion implantation, via diffusion, or any other doping method that achieves doping of existing oxide 105 and can be made compatible with back end of line processes. Reference to “within the vertical span of the metal stack” herein shall be understood to refer to locations vertically at a level at or above the lowest portion of the metal stack and vertically at a level at or below the highest portion of the metal stack and include locations lateral to the metal material of the metal stack.

In the back end of line processes, oxide 105 is deposited and then doped with phosphorous (P). Optical waveguides 120 a, 120 b could be formed from a thick oxide doped once or from a process of depositing and doping several thin oxide layers. In other embodiments the doping agent includes any of B, F, Al, Ti, As, P, Er, Ni, Si, Cu, Zn, Ge, N, Zr, Nd, and Yb. Doping agents and the doping process are chosen in order to create waveguides 120 a, 120 b with a higher index of refraction than the surrounding oxide 105. In one embodiment, once a doped optical waveguide 120 a has been formed within the oxide 105, the oxide 105 is etched and a metal layer 108 a at the same layer as the optical waveguide 120 a is deposited. In another embodiment, prior to doping to form the optical waveguide 120 a, the oxide 105 at the same layer as the optical waveguide 120 a is etched and the metal layer 108 a is deposited. In the embodiment illustrated in FIG. 1 the optical waveguides 120 a, 120 b form an edgecoupler capable of large mode fiber coupling.

A heavy doping of the oxide 105 provides confinement of an optical mode with low loss, a technique that has been used in glass planar lightwave circuit (PLC) technology. Multiple doped waveguides may be used to move the optical mode near to the surface of the chip so that a large mode may be achieved with low substrate loss, an advantage generally obtained by building optical devices within the vertical span of the metal stack. Moreover, depending upon the distance between the optical waveguides 120 a, 120 b and the silicon layer 106, optical devices can be formed directly under the optical waveguides 120 a, 120 b without the risk of unwanted coupling or loss to the silicon layer. The optical waveguides 120 a, 120 b, are not subject to the high confinement limitations applicable to optical devices fabricated from the silicon layer 106.

With reference to FIG. 2, an example of using the silicon nitride (SiN) etch stop layers in standard CMOS back end of line fabrication process to create integrated optical devices will now be described.

An integrated optical chip 200 includes a silicon substrate or silicon handle 202 on which is formed the buried oxide (BOX) layer 204. A silicon layer 206 is formed on top of the buried oxide layer 204, much of the silicon layer 206 of which is utilized for fabrication of semiconductor devices therein, which devices are connected to each other and external contacts with use of a metal stack including metal vias 210 a, 210 b connecting metal layers 208 a, 208 b in the stack. Above the silicon layer 206 are various oxide layers 205 which have been deposited during the metal layer fabrication process. Etch stop layers 220 a, 220 b, 220 c, 220 d utilized in the fabrication process to form the metal stack are typically made of silicon nitride (SiN) or other suitable etch stop material. In the embodiment shown in FIG. 2, the material is compatible with optical device fabrication, such as SiN or poly-silicon. A portion of a first etch stop layer 222 a as well as a portion of the second etch stop layer 222 b are utilized to form an optical device, namely, a vertical coupler 222 to optically couple light between a portion of the silicon layer 206 a in which an optical device has been formed with an arrayed waveguide grating (AWG) 224 formed from an etch stop layer 220 c, 224 above the vertical coupler 222.

Although the AWG 224 of the embodiment of FIG. 2 is in the third SiN layer from the silicon on insulator layer 206, in other embodiments the AWG is formed in any other etch stop layer used to fabricate the metal stack. In the CMOS back end of line process, thin SiN layers are deposited before etching oxide for metal. In the embodiment illustrated in FIG. 2, additional masks are used to etch the SiN layer to define the waveguides of the AWG 224, and the vertical coupler 222 a, 222 b, and thereafter oxide is deposited on top of the SiN layers. Using masks which define the corresponding metal layer interconnects of the metal stack, the oxide is etched followed by metal deposition.

Forming an AWG 224 in silicon nitride of an etch layer in the back end of line process has an advantage over fabricating it in the silicon on insulator layer. Silicon nitride has a lower index of refraction compared to silicon, so the coherence length in a waveguide in SiN is longer than that in a similarly sized and shaped waveguide in silicon. The performance of an AWG 224 formed in silicon nitride will be increased due to improved predictability of phase shifts in the optical mode traveling in the waveguides. As with the embodiment described in association with FIG. 1, the device is in a layer that was deposited in the back end of line fabrication process and the distance between the AWG 224 and the silicon handle 202 is large enough to prevent substrate loss. Moreover, because the distance between the AWG 224 and the devices on the silicon on insulator layer 206 can be more than 4 micrometers, the light in the AWG 224 will not couple to the silicon layer 206. This allows fabrication of optical circuits directly beneath the AWG 224, reducing the space and cost on the chip.

Although the embodiment depicted in FIG. 2 utilize portions of etch stop layers for optical device fabrication within the vertical span of the metal stack, chemical mechanical planarization (CMP) stop layers made for example of SiN, and/or other dielectric material layers used in fabricating the metal stack, such as various layers of SiON, are contemplated for optical device fabrication.

With reference to FIG. 3 an example of deposited SiN (or amorphous silicon) optical devices fabricated between two metal layers during back end of line fabrication processes will now be described.

An integrated optical chip 300 includes a silicon substrate or silicon handle 302 on which is formed the buried oxide (BOX) layer 304. A silicon layer 306 is formed on top of the buried oxide layer 304, much of the silicon layer 306 of which is utilized for fabrication of semiconductor devices therein, which devices are connected to each other and external contacts with use of a metal stack including metal vias 310 a, 310 b connecting metal layers 308 a, 308 b in the stack. Above the silicon layer 306 are various oxide layers 305 which have been deposited during the metal layer fabrication process. Etch stop layers 320 a, 320 b, 320 c, 320 d utilized in the fabrication process to form the metal stack are typically made of silicon nitride (SiN) or other suitable etch stop material. In the embodiment shown in FIG. 3, the material is compatible with optical device fabrication, such as SiN. A portion of a first etch stop layer 322 a as well as a portion of the second etch stop layer 322 b are utilized to form an optical device, namely, a vertical coupler 322 to optically couple light between a portion of the silicon layer 306 a in which an optical device is formed with a multimode interference coupler (MMI) 340 or other optical device formed in a SiN or a-Si layer deposited vertically between two metal layers 308 a, 308 b and between etch stop layer 320 c above the vertical coupler 322 and the upper etch stop layer 322 b of the vertical coupler 322.

Although the MMI 340 of the embodiment of FIG. 3 is between the third and fourth etch stop layers 320 b, 320 c, in other embodiments the MMI is formed between any other two consecutive etch stop layers used to fabricate the metal stack. In the embodiment illustrated in FIG. 3, after the first metal layer 308 a has been completed, and before oxide etching for making metal vias 310 b, SiN or a-Si is deposited on top of a layer of the oxide 305 and etched to leave a desired structure and thereby form optical circuits such as MMI 340. Oxide cladding is deposited on top of the SiN or a-Si layer, and thereafter vias 310 b are fabricated, followed by fabrication of the rest of the metal stack above it.

Forming an MMI 340 by deposition during the back end of line process has an advantage over fabricating it in the silicon on insulator layer. Back end of line process fabrication is more flexible in terms of which materials can be deposited thereby allowing to better materials matching between different chips. As with the other embodiments described in association with FIG. 1 and FIG. 2, the device is in a layer that was deposited in the back end of line fabrication process and the distance between the MMI 340 and the silicon handle 302 is large enough to prevent substrate loss. Moreover, because the distance between the MMI 340 and the devices on the silicon on insulator layer 306 can be more than 4 micrometers (given an appropriate choice of metal layers for deposition therebetween), the light in the MMI 340 will not couple to the silicon layer 306. This allows fabrication of optical circuits directly beneath the MMI 340, reducing the space and cost on the chip.

Although the embodiment depicted in FIG. 3 illustrates deposition of an optical device between etch stop layers within the vertical span of the metal stack, fabrication of optical devices between any one or more of etch stop layers, chemical mechanical planarization (CMP) stop layers and other dielectric material layers used in fabricating the metal stack are contemplated.

In other embodiments, silicon oxynitride (SiON), poly-silicon, silicon-germanium (SiGe), or germanium (Ge) are deposited on top of the oxide 305 and etched to form the optical device 340.

In specific variations of the embodiment depicted in FIG. 3, the optical device 340 is formed of the same material as the surrounding oxide 305, however with use of a deposition process utilizing alternate deposition conditions, such as a lower deposition rate, than that used to deposit the surrounding oxide 305, in order to create a denser material having a higher refractive index than the oxide 305 surrounding the optical device 340. In one such variant of the embodiment of FIG. 3, the oxide 305 and the optical device 340 both comprise SiO₂.

Higher indices can also be achieved through other known techniques such as processes including chemical vapor deposition (CVD) or flame hydrolysis deposition to form, for example, a silicate glass (comprising SiO₂ and any of P₂O₅, B₂O₃, F, Al₂O₃, As₂O₃, GeO₂, N₂, TiO₂, ZrO₂, Nd₂O₃, Er₂O₃, and Yb₂O₃) which has a higher index of refraction than the surrounding SiO₂.

Deposition methods in accordance with the embodiment depicted in FIG. 3 include generally methods of deposition such as CVD, plasma-enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), and Flame Hydrolysis deposition or any other method of deposition which is compatible with back end of line fabrication processes.

Deposition materials in accordance with the embodiment depicted in FIG. 3 include generally any materials compatible with any methods of deposition on top of an oxide 305 compatible with back end of line fabrication processes, which are also suitable for optical device fabrication, including any of SiN, a-Si, SiON, poly-silicon, SiGe, Ge, SiO₂, P₂O₅, B₂O₃, F, Al₂O₃, As₂O₃, GeO₂, N₂, TiO₂, ZrO₂, Nd₂O₃, Er₂O₃, and Yb₂O₃.

As described hereinabove fabrication of integrated optical devices in both the silicon layer of the front end and integrated optical devices formed in the backend of line fabrication process preferably involve some form of integrated on chip optical coupling between them.

With reference to FIG. 4A, FIG. 4B, and FIG. 4C an example coupling between optical devices formed in the standard silicon front end and optical devices fabricated as part of the back end of line fabrication process will now be described.

FIG. 4A is a vertical cross-section of the simulation region depicted in FIG. 4C, which consists of one silicon front-end layer 406 and two back-end of line process layers 422 a, 422 b. Between them is deposited oxide 405. FIG. 4B is the top view of the vertical coupler that consists of two inverse tapers 422 a 406. FIG. 4C depicts the simulated electrical field of an optical signal propagating through the waveguides 422 a, 422 b, 406 depicted in FIG. 4A and FIG. 4B. As can be seen clearly in FIG. 4C, the light is coupled from one layer to another through the vertical coupler.

Although the particular example embodiment depicted in FIG. 4A, FIG. 4B, and FIG. 4C possesses a vertical coupler utilizing two tapers, other kinds of vertical coupling, including those utilizing grating couplers or rings, for example, are also contemplated.

With reference to FIG. 5 an example vertical coupler coupling an optical device built in the front end with an optical device formed in the back end of line fabrication process will now be described.

An integrated optical chip indicated by numeral 500 includes a silicon substrate or silicon handle 502 on which is formed the buried oxide (BOX) layer 504. A silicon layer 506 is formed on top of the buried oxide layer 504, much of the silicon layer 506 of which (not shown) is utilized for fabrication of semiconductor devices therein, which devices are connected to each other and external contacts with use of a metal stack including metal layer 508. Above the silicon layer 506 are various oxide layers (not shown) which have been deposited during the metal layer fabrication process. Etch stop layers 520 a, 520 b utilized in the fabrication process to form the metal stack are typically made of silicon nitride (SiN) or other suitable etch stop material. In the embodiment shown in FIG. 5, the etch stop material is compatible with optical device fabrication, such as SiN. A tapered portion of the silicon layer 506 and a portion of a first etch stop layer 522 a form a first vertical coupler 522I while a different portion of the first etch stop layer 522 a as well as a tapered portion of the second etch stop layer 522 b are utilized to form a second vertical coupler 522II. These vertical couplers 522I, 522II serve to optically couple light between the silicon layer 506 utilized for optical devices with the etch stop layer 522 b used to form an optical device 522 b which happens to be an edge coupler for coupling light with an optical fiber 540.

Although the embodiments above have provided specific examples of integrated optical devices formed during back end of line processes, formed of specific materials at specific locations it should be understood that in accordance with what is disclosed herein, all optical devices compatible with back end of line process fabrication are contemplated. As such, in addition to the edge couplers, AWG, MMI, and vertical couplers, grating couplers, splitters, directional couplers, polarization splitters, polarizers, echelle gratings, thermal phase shifters, and other various optical devices are contemplated.

Although the embodiments above have made specific reference to particular materials utilized in the etch stop, CMP stop and other layers and for fabrication of optical devices through deposition or doping materials, all materials compatible with back end of line process fabrication suitable for optical devices are contemplated.

Although the embodiments above have provided specific examples of particular fabrication processes, layers, and techniques, all processes compatible and possible for inclusion in back end of line processes generally during fabrication of the metal stack, are contemplated. For example, the materials can be placed in the backend using a number of different processes rather than just a single process. The fabrication process can utilize a different numbers of masks, more process steps, and/or improved process control, as necessary.

Although the embodiments above have been described with reference to existing backend layers, additional layers can be added during back end of line processing.

While particular implementations and applications of the present disclosure have been illustrated and described, it is to be understood that the present disclosure is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations can be apparent from the foregoing descriptions without departing from the spirit and scope of an invention as defined in the appended claims. 

What is claimed is:
 1. An optical device, comprising: a substrate; a silicon device layer on the substrate, the silicon device layer including at least one optical device; a vertical stack of metal layers being located over the silicon device layer and electrically connecting between external contacts and the silicon device layer; a vertical stack of silicon nitride layers, the metal layers being between the silicon nitride layers; and an optical coupler comprising portions of at least ene some of the silicon nitride layers, the optical coupler being for coupling light into or out of the silicon device layer.
 2. The device according to claim 1, further comprising: a first oxide layer on the silicon device layer, a first of the silicon nitride layers being on the first oxide layer; a second oxide layer on the first of the silicon nitride layers stop layer, the second oxide layer including a first of the metal layers therein, a second of the silicon nitride layers being on the second oxide layer; and a first metal via connecting the first of the metal layers to the silicon device layer.
 3. The device according to claim 2, wherein the optical coupler comprises a portion of the first of the silicon nitride layers, and a portion of the second of the silicon nitride layers.
 4. The device according to claim 3, wherein at least one of the silicon nitride layers comprises a tapered portion in the optical coupler.
 5. The device according to claim 2, further comprising: a third oxide layer on the second of the silicon nitride layers, a third of the silicon nitride layers being on the third oxide layer; and a fourth oxide layer on the third of the silicon nitride layers; wherein the optical coupler comprises a portion of the third of the silicon nitride layers; and wherein a second of the metal layers is in a first portion of the fourth oxide seventh layer; and further comprising a second metal via connecting the second of the metal layers to the silicon device layer.
 6. The device according to claim 5, wherein the third waveguide comprises an arrayed waveguide grating (AWG).
 7. The device according to claim 6, wherein the AWG is more than 4 micrometers from the device layer.
 8. The device according to claim 5, wherein the third waveguide comprises a multimode interference coupler.
 9. The device according to claim 1, wherein the optical coupler is an edge optical coupler.
 10. The device according to claim 1, wherein the optical coupler is a vertical optical coupler. 